SDRAM Explained

Synchronous DRAM (SDRAM) was originally a lower cost alternative to VRAM. It is synchronized to the system clock (that is, the external CPU frequency), taking memory access away from the CPU's control; internal registers in the chips accept a request, and let the CPU do something else while the data requested is assembled for the next time it talks to the memory, as the memory knows when the next cycle is due because of the synchronization.

In other words, SDRAM works like standard DRAM, but includes interleaving, synchronization and burst mode, so wait states are virtually eliminated (SDRAM DIMMs also contain two cell banks which are automatically interleaved). It’s not actually faster than DRAM, just more efficient; although the chips are rated at 10 ns, they are not used at that speed - typically, between 20-50 ns is more like it, since the smaller figure only refers to reads from sequential locations in bursts - the larger one refers to the initial data fetch.

Data  bursts are twice as fast as with EDO (above), but this is slightly offset by the organization required. The peak bandwidth of 133 SDRAM is about 33% higher than that of 100.

Registered DIMMs contain registers on board, which re-drive the signals, meaning you can have more chips. SLDRAM uses an even higher bus speed and a packet system. However, with a CPU running at 4 or 5 times the memory speed, even SDRAM is finding it hard to keep up, although DDR (Double Data Rate) SDRAM doubles the memory speed by using the rising and falling edges of the clock pulse, and has less latency than RAMBUS, giving it a slight edge.

Performance wise, SDRAM only really comes into its own with a memory bus above 75 MHz. Hitachi have developed a way of replacing the capacitor in DRAM with a transistor attached to the MOSFET, where a 1 or 0 is represented by the presence (or not) of electrons between its insulating layers. This means low power requirements, hence less heat, and speed.