Floppy 3 Mode Support
This is for the Japanese standard floppy, which gets 1.2 Mb onto a 3.5" diskette. Normally disable, unless you have one installed.

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Automatic configuration
When this is Enabled, the BIOS sets its own values for some items, such as the Bus Clock Speed, Fast Cache Write Hit, Fast Cache Read Hit, Fast Page Mode DRAM, DRAM Wait State, DMA CAS Timing Delay, Keyboard Clock, etc (the items will vary between motherboards). The important thing to note is that your own settings will be ignored, so disable this one if you want to play, or have to change any of the above settings to accommodate a particular card, such as a Bus Logic BT-445S on a 50 MHz 486 system.

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IDE 32-bit Transfer
Many local bus interfaces can combine two 16-bit words into a 32-bit doubleword when reading data to and from the disk, particularly useful with bus mastering. This is often called 32-bit access, though it's really 32-bit host bus transfers. Either way, more efficient use is made of the bus and CPU, so this may or may not make much difference if you don’t actually have a bottleneck. This is not the same as Windows' 32-bit features, which are also misnamed as they just work in protected mode.

If disabled, 16-bit data transfers are used, so performance will be less.
If enabled, hard disk data is read twice before request signals are sent to the CPU.

This setting can only be enabled if IDE Prefetch Mode is also enabled (below). As far as AMI are concerned, the WinBIOS will initialize the hard disk firmware for 32-bit I/O, assuming your hard disk is capable—it refers to the new release of high performance Mode 4 drives.

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Hidden Refresh
When CAS is low, RAS is made high, then low. Since CAS is low before RAS, you get a CBR refresh. The "hidden" part comes from the fact that data out stays on the line while refresh is being carried out, otherwise this is the same as CBR. If CAS is hidden, you can eliminate a CPU cycle, but the CPU can also maintain the cache status if the system starts power saving. Best system performance is naturally obtained with this enabled, but expect to disable it if you are using 4Mb DRAMs (or certain SIMMs), or you get problems. Most of the effects of this setting are masked if you have a cache.

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Non-cacheable Block-1 Size
Depending on the chipset, this concerns memory regions (including ROMs) not within the 32-bit memory space, e.g. those on 16-bit expansion cards on the expansion bus (video cards, caching disk controllers, etc) that should not be cached because RAM on them is updated by the card itself, and the main board cache controller can't tell if the contents change. These devices communicate as if they were DRAM memory (that is, they are memory-mapped), which means they need to react in real time and would be seriously affected by caching. You would also use this to lock out any ROMs you can't otherwise disable caching for; certain caching IDE controllers use a space at the top end of base memory for hard disk details, and therefore cause timing problems if the information is cached; symptoms include consistent bad sectors when formatting floppies, or a scrambled hard disk.

Also, video cards sometimes use a 1 Mb area in the 16 Mb address space of the ISA bus so they don't have to bank switch through the usual 64K page (early Video Blaster cards are notable for this requirement; they won't work in a machine with more than 15 Mb RAM).

You might get a choice of System Bus or Local DRAM. The former produces a hole in Local DRAM. NCB areas can be separate, contiguous or overlapped. With Asustek cache controllers, include the video buffer at A000-BFFF. This setting is closely linked to the next.

Note: Some chipsets (e.g. SiS) use this to define non-cacheable regions only in local DRAM; with them, memory on PCI or VESA add-ons is always non-cacheable. Where memory space is occupied by both local DRAM and an add-on card, the local DRAM will take priority (as does VESA over PCI), so disable this to allow access or give priority to the card.

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AT Cycle Wait State
This figure represents the number of wait states inserted before an operation is performed on the AT bus. The effect is to lengthen the I/O cycle for expansion cards that have a tight tolerance on speed, such as high-end graphics cards, or you might be overclocking and the ISA bus is tied to the PCI bus  speed and you can't change it. Again, for expansion cards with special requirements (you may get separate options for 16-bit and 8-bit transfers).

The higher the delay in bus timing, the slower your system will run; 1 wait state can half the bus speed, and you will also need to set a higher DMA wait state. To avoid confusion, a private message is sent along the data bus for 16-bit cards, before data is sent. The high part of the target address is sent out  first, so 16-bit cards are alerted as to where instructions are headed. As these are sent out over the extra 4 address lines on the extended bus  (20-23), the only information the cards really get is which of the 16 possible megabytes is the destination, so 3 of the original 8-bit lines are  duplicated (17-19), narrowing it down to the nearest 128K. Once a card decides the message is for itself, it places a signal on memcs16, a line on the extended bus, which triggers a 16-bit signal transfer  (without the signal, the message is sent as 8-bit). When the CPU sees memcs16, it assumes the current access will be to a 16-bit device, and begins to assemble data so any mismatches are transparent to the CPU and adapter card. The trouble is that there's no specification governing the amount of time between the advance notice and the actual transfer, and some cards don't request 16-bit transfers quickly enough, so it gets its data as 8-bit, hence confusion, and the need for wait states. VGA cards can switch into 8-bit mode automatically, but many others cannot. I/O operations on the bus generally have an extra wait state compared to memory.

Extra AT Cycle Wait State
See above.

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Cache Read Hit Burst 
Burst Mode is a 486 function for optimising memory fetches if you need to go off-chip, which works by reading groups of four double-words in quick succession, hence burst. The first cycle has to cope with the start address as well as its data, so it takes the longest (the other three addresses are deduced). Once the transfer has been started, 4 32-bit words could therefore move in only 5 cycles, as opposed to 8, by interleaving the address and data cycles after the first one. For this, you need fast RAM capable of Page Mode. This setting determines the number of cycle times to be inserted when the CPU reads data from the external (Level 2) cache, when it can't catch up with the CPU (you may see similar figures allocated to L1 cache, on chip). 

The Secondary Cache Read Hit can be set to 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 (3-1-1-1 means the first 32-bit word needs three clock cycles and the remainder need one, giving a total of 6 clock cycles for the operation). Performance is affected most by the first value; the lower the better; 2-1-1-1 is fastest. You can alter it with the Cache Read Hit 1st Cycle WS setting. This will have no effect if all the code executes inside the chip. For example, the setting for 33 MHz may need to be changed to 3-2-2-2 if you only have 128K, or with Asynchronous SRAM. The following may be useful as a starting point (1 bank cache/2 banks cache): Item 20 MHz 25 MHz 33 MHz 50 MHz SRAM Read Burst Control 3222/2111 3222/2111 3222/3111 3222 SRAM Write Wait States 0W 0W 1/0W 1W DRAM Write Wait States 0W 0W 1W 1W DRAM Read Wait States 1W 2W 2W 3W RAS# to CAS# Delay 1 Sysclk 1 Sysclk 1 Sysclk 2 Sysclk Pentiums can perform Burst Writes as well as Burst Reads, so you might have a separate selection for these. 4-1-1-1 is usually recommended.

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Cache Burst Read Cycle Time 
See Cache Read Hit Burst. Automatically set to 2T if only one bank of Level 2 cache is available, that is, the whole cycle takes place inside 2 T-states. 

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DRAM Page Mode Operation
Page mode allows faster timing on consecutive memory accesses within a single DRAM page. Mostly, page mode is invoked automatically if the DRAM supports it.

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CPU to DRAM Page Mode
Determines whether a DRAM memory page is held open after a memory access, as those to open pages can be between 30-40% faster than to closed pages, because they don't need pre-charging. 
Enabling this keeps all pages open. Disabling only opens them during burst operations, etc, when subsequent accesses will be to the same page.

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Force Updating ESCD
If enabled, the ESCD area in Upper Memory (for PnP information concerning IRQ, DMA, I/O and memory) will be updated once, then this setting will be disabled automatically for the next boot. 

Use if you have installed a new card and the subsequent reconfiguration causes a serious conflict of resources (the OS may not boot as a result). The BIOS will then reallocate everything.

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S.M.A.R.T. for Hard Disks
Self-Monitoring Analysis & Reporting Technology, a feature of EIDE. Allegedly allows a drive to monitor itself and report to the host (through management software) when it thinks it will fail, so network managers have time to order spares. In fact, the management software sits between the BIOS and the hard drive and allows the BIOS to look at the data and decide whether or not to give you warning messages. This has nothing to do with performance, but convenience. Unfortunately, although Win 95 OSR2 and OS/2 (Merlin) are SMART aware, many failures cannot be sensed in advance. Some utilities can check the status of a drive - Micro House EZ-S.M.A.R.T. and Symantec S.M.A.R.T. Doctor.

Since this system allows the monitoring of hard drives over a network, you will get extra packets not necessarily controlled by the operating system - if you get mysterious reboots and crashes, disable this. If you get problems with Win 98, check out article Q199886 in the MSN.

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