The RAM Guide
(Extended Data Output)
is an advanced version of fast page mode (often called Hyper Page Mode, but see below), which can be up to 30% better and only cost 5% more. Single-cycle EDO carries out a complete memory transaction in 1 clock cycle by overlapping stages that otherwise would take place separately; for example, precharging can start while a word is still being read, and sequential RAM accesses inside the same page take 2 clock cycles instead of 3, once the page has been selected, because the data output buffer
is kept open rather than being turned off, as it would be with Fast Page Mode Memory (see Wait States, below). It is assumed that if one address is needed, others nearby will be, too, so the previous one is held open for a short while.
In other words, output is not turned off when CAS goes high (i.e. turned off, or has stopped allowing addresses to be moved to the device). In fact, data can still be output after CAS has gone high, then low again (and another cycle has therefore started), hence the name, Extended Data Out; data remains available until that from the next access begins to appear.
A memory address can hold data for multiple reads.
This means you can begin precharging CAS whilst waiting for data. The end result is that cycle time is cut by around 20% and data is available longer. The really neat thing is that CAS can go high before data appears (well, maybe not to you and me, but it is to a motherboard designer). EDO is only faster with memory reads, though; writes take place at the same speed as Fast Page Mode. In any case, it only works if your cache controller supports pipeline burst transfer. When it does, it effectively reduces 60 ns RAM to 25 ns, giving you a 40 MHz CPU, without wait states.
The combination of DRAM plus an external latch between it and the CPU (or other bus mastering device), would look like EDO DRAM because the external latch can hold the data valid while the DRAM CAS goes high and the address is changed. It is simpler and more convenient to have the latch inside the DRAM, hence EDO. As it replaces a Level 2 cache and doesn't need a separate controller, space on the motherboard is saved, which is good for notebooks. It also saves on battery power.
In short, EDO gives increased bandwidth due to shortening of the page mode cycle (and 3-2-2-2 bursts rather than 7-4-4-4)-an entire block of memory can be copied to its internal cache and a new block collected while the CPU is accessing it. It appears to be able to run (unofficially) above 66 MHz. Don't get 70 ns EDO, as it will be difficult to upgrade the CPU.
BEDO, or Burst Extended Data Out
is as above, but has a pipeline stage and a 2-bit burst counter that can read and write large streams of data in 4-cycle bursts for increased performance, based on the addresses being dealt with in the first cycle. The pipelining system can save 3 cycles over EDO. It is designed to
achieve 0 wait state performance at 66 MHz and upwards, as it brings your 60 ns RAM down to 15 ns (again, see chart above). The relevant speeds for Fast
Page Mode and EDO are 25 and 40, respectively, and the increase in performance 100% and 40%.
replaces standard DRAM and the L2 cache on the motherboard, typically combining 15ns SRAM inside 35ns DRAM. Since the SRAM can take a whole 256 byte page of memory at once, it gives an effective 15ns access speed when you get a hit (35ns otherwise), so system performance is increased by around 40%. The L2 cache is replaced with an ASIC chip to sort out chipset/memory requirements (an ASIC chip is one specially made for the purpose). EDRAM has a separate write path that accepts and completes requests without affecting the rest of the chip.
NEC is producing
which, they say, gives 2ns access speed. It interconnects with a system called RAMBUS, which is a
narrow, but ultra high speed, local memory bus, made with CMOS technology. It also uses a packet technique for data transfer, rather than coping with individual bytes. BIOS support is needed in the chipset for this to work as system memory.
Although its data transfer rate is twice that of SDRAM (see below), it suffers from latency problems, which reduces the performance edge, and is more expensive. RDRAM has its own communications bus with a separate controller that mediates between it and the CPU, using a relatively narrow serial connection 16 bits wide with separate lines for
row and column signals. It runs at 400 MHz and uses both sides of the clock cycle. As the signal lines are separate from the data lines, you can be reading or writing at the same time as preparing for a second or even a third operation.
The memory itself uses 184-pin RIMMs, which are similar to DIMMs but with a heat sink, required because the chips are more tightly packed together, even though they require less power and generate less heat. The 820 chipset supports only 2 RAMBUS modules from mixed suppliers. It will work better with the Pentium IV. The various speeds available are PC600, PC700 and PC800.
Virtual Channel RAM
is a development of SDRAM (see below), also from NEC, using standard DIMM sockets. Because of its low latency and speed (133 MHz), it is a very good choice, and is supported by VIA's Apollo Pro Plus chipset.
, created by Samsung, is dual ported, like VRAM, but costs about 20% less and is 50% faster with around 25% more bandwidth (dual porting means reading and writing takes place at the same time). It runs at 50 MHz and can transfer blocks and support text and pattern fills. In other words, some graphics functions are built in, so look for these on graphics cards. VRAM, by the way, is used on graphics cards that need to achieve high refresh rates; DRAM must use the same port as it does for data to do this, where VRAM uses one port to refresh the display and the other to change the data. Otherwise, it is generally the same speed as DRAM. SGRAM, or Synchronised Graphics RAM, is single ported, using dual banks where 2 pages can be opened at once. It has a block write system that is useful for 3D as it allows fast memory clearing.
was originally a lower cost alternative to VRAM, using a 168-pin DIMM. It is synchronised to the system clock (that is, the external CPU frequency), taking memory access away from the CPU's control; internal registers in the chips accept a request, and let the CPU do something else while the data requested is assembled for the next time it talks to the memory, as the memory knows when the next cycle is due because of the synchronisation. In other words, SDRAM works like standard DRAM, but includes interleaving, synchronisation and burst mode, so wait states are virtually eliminated (SDRAM DIMMs also contain two cell banks which are automatically interleaved). It's
not actually faster than DRAM, just more efficient. In fact, the main specification for SDRAM when shopping is its access speed, which originally was 12 or 10 ns, latterly becoming 8 ns, which relates to the PC 100 standard. PC 133 uses 7.5 ns.
Data bursts are twice as fast as with EDO (above), but this is slightly offset by the organisation required. The peak bandwidth of 133 SDRAM is about 33% higher than that of 100. Registered DIMMs are meant for mission critical systems where the data must arrive in the proper format. They contain a register, or buffer chip, between the memory controller and chips on the DIMM to delay everything by one clock
cycle to ensure everything is there. Buffered memory, which is nearly the same, redistributes the addresses and reduces the load on the memory clock, so you can have more chips - indeed, the buffer is there to handle the large electrical loads that are caused by
having large amounts of memory. In the trade, Major on Third chips are those from a major manufacturer used on third party motherboards. Major on Major means they are used on their own.
uses an even higher bus speed and a packet system. However, with a CPU running at 4 or 5 times the memory speed, even SDRAM is finding it hard to keep up, although DDR (Double Data Rate) SDRAM doubles the memory speed by using the rising and falling edges of the clock pulse, and has less latency than RAMBUS, giving it a slight edge. It also uses a lower voltage and 184-pin DIMMs. Because of the timing difficulties, different chipsets treat DDR in different ways, so be careful when changing motherboards - probably about 40% of DIMMs will work for any given board. It is specified as PC1600 or PC2100 (that is, the peak data rate in Mbytes/sec).
Hitachi have developed a way of replacing the capacitor in DRAM with a transistor attached to the MOSFET, where a 1 or 0 is represented by the presence (or not) of electrons between its insulating layers. This means low power requirements, hence less heat, and speed.
This is an article from Phil
Croucher, author of "The
BIOS Companion" Phil has a way of explaining in "plain"
English. The information is well presented and is well above A+ standard.