|
|
S2K I/O Compensation
Bank X/Y DRAM Timing
SDRAM SRAS Precharge Delay: tRP
CPU Level 2 Cache ECC Checking
System Monitor Setup
- Fan Speed
- Voltage Values
- VCCVID(CPU) Voltage,
VTT (+1.5V)Voltage
- /O Plane Voltage
- Core Plane Voltage
- Plane Voltage
CPU
to PCI Byte Merge
WAIS
WAN
Celeron
Cyrix A20M Pin
Boot
Sector Virus Protection
ChipAway
Virus On Guard
CPU
Internal Core Speed
CPU Core: Bus Freq. Multiple
CPU
Clock Failed Reset
ISA
IRQ 9,10,11
MMX
Fast Cache Read/Write
Flush 486 Cache Every Cycle
Byte
Merging
ISA Master Line Buffer
Configuration Mode
LPT Extended Mode
Parallel Port EPP Type
Keyboard Reset Control
Keyboard Clock Select
Force Updating ESCD
SDRAM Precharge Control
SDRAM CAS Latency Time
MPS Version Control For OS
PCI Burst Write Combine
Assign IRQ for VGA
PCI Mem Line Read
Spread Spectrum Modulated
Decoupled Refresh Option
CPU-To-PCI
Write Posting
Time
Dilation
Open Sesame
Recovering A Corrupt BIOS
Setting Up For Performance
Video ROM Shadow C000, 32K
Video BIOS Shadow
Floppy 3 Mode Support
Automatic configuration
IDE 32-bit Transfer
Non-cacheable Block-1 Base
Non-cacheable Block-1 Size
Reset Configuration Data
Use Multi-Processor Specification
Using IRQ
|
DOS Flat Mode
Memory
Termination
SDRAM Addr A Clk Out Drv
SDRAM Configuration
Fast R-W Turn Around
PCI Delayed Transaction
AGP
Fast Write Transaction
Motherboard
Layout
Clock Spread Spectrum
Byte Merging
PCI Dynamic Bursting
PCI #2 Access #1 Retry
Soft-off
by PWR-BTTN
Monitor
Mode
Speed Model
Byte
Merge Support
WASHITO
Wavelength Multiplexing
Current
CPU Temperature
Cyrix
Pin Enabled
Virus
Warning
Report no FDD for Win 95
CPU
L2 cache ECC Checking
CPU
Host Bust Frequency
CPU Core Voltage
CIH
Buster Protection
Init
Display First
Read/Write Leadoff*
SIO
Master Line Buffer
ISA Line Buffer
Cache Read Hit Burst
Cache Burst Read Cycle Time
SRAM Read Timing
DRAM Page Mode Operation
CPU to DRAM Page Mode
Fast Strings
Power Management
Smart Battery System
PM Control by APM
IDE Standby Power Down Mode
Standby Mode Control
S.M.A.R.T. for Hard Disks
SDRAM RAS to CAS Delay
SDRAM RAS Precharge Time
AGP
PCI Memory Burst Write
PCI Mem Line Read Prefetch
Novell Keyboard Management
Fast Gate A20 Option
Turbo Switch Function
Gate A20 Emulation
I/O Cmd Recovery Control
Single ALE Enable
E0000 ROM belongs to AT BUS
AT Cycle Wait State
Extra AT Cycle Wait State
16-bit Memory, I/O Wait State
8-bit Memory, I/O Wait State
|
