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Weekly Tweaks Archive

Fast Cache Read/Write
Usually used if you have two banks of external SRAM cache chips, that is, 64 or 256K. It's similar to Page Mode for DRAM.


Flush 486 Cache Every Cycle
Enabled, flushes the internal 8K cache of the 486 every cycle, which seems to defeat the object somewhat. 
Disable this.


Read/Write Leadoff*
Before data can be accessed, the core logic must issue the memory address signal, the column address strobe (CAS) signal and the row address strobe (RAS) signal to the DRAM. However, these signals are not issued at the same time. The time difference between them is called the lead-off time, and often equates to the timing of the first cycle in a burst. It varies for read and write actions, depending on the DRAM-some may require longer delays.


Byte Merging
This exists where multiple writes to non-contiguous memory addresses are merged into one PCI-to-memory operation by the host controller, letting devices sort out the ones they want, which increases bus throughput and hence performance for devices that support it-not all PCI video cards do, so enable unless you get bad graphics (this setting is intended to improve video performance). When enabled, the controller checks the CPU Byte Enable signals (8 of them) to see if data from the PCI bus can be merged. See also Byte Merge Support (next) and CPU-PCI Byte Merge.


ISA Master Line Buffer
ISA master buffers are designed to isolate slower ISA I/O operations from the PCI bus for better performance. 
Disabled means the buffer for ISA master transaction is in single mode. 
Enabled means it is in 8-byte mode increasing the ISA master's performance. See also ISA Line Buffer, below.

SIO Master Line Buffer
As above, found on Pentium Pro machines.


ISA Line Buffer
The PCI-to ISA bridge has an 8-byte bi-directional line buffer for ISA or DMA bus master memory reads from or writes to the PCI bus. When this is enabled, an ISA or DMA bus master can pre-fetch two double words to the line buffer for a read cycle.


CPU L2 cache ECC Checking
If enabled, data is checked as it passes through the L2 cache, which reduces performance slightly. However, you must be running a fastish PII or above to see any difference.


You can insert a delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals when SDRAM is written to, read from or refreshed - in other words, this determines how quickly memory is accessed. The lower the number, the faster the performance at the expense of stability.


SDRAM RAS Precharge Time
Controls the memory timing by setting the number of cycles the RAS needs to accumulate its charge before SDRAM refreshes. Reducing this too low affects the ability to retain data.


SDRAM Precharge Control
See also above. If disabled, all CPU cycles to SDRAM will result in an All Banks Precharge Command on the SDRAM interface. Enabled is best for performance at the expense of stability.


SDRAM CAS Latency Time
Optimizes the speed at which data is accessed in a column by defining CAS latency time in 66 or 100 MHz clocks, depending on the memory bus speed - it controls the time delay (in CLKs) before SDRAM starts a read command after receiving it. Because reading data in a row is twice as fast, reducing this number can help quite a bit at the expense of stability, but the higher it is, the faster you can run the machine, if the memory is capable.


MPS Version Control For OS
This specifies the version of the Multiprocessor Specification (MPS) to be used. Version 1.4 has extended configuration tables to improve support for multiple PCI bus configurations and provide future expandability - use this for NT, and possibly Linux. It is also required for a secondary PCI bus to work without the need for a bridge. Leave it as 1.1 for older server Operating Systems.


Report no FDD for Win 95
Set to Yes if using Windows 95/98 without a floppy to release IRQ6 (this is required to pass Windows 95/98's SCT test). Also disable the Onboard FDC Controller in the Integrated Peripherals screen.


PCI Burst Write Combine
This is meant to speed up video processing by up to about 15%, as many writes to video memory are with individual pixels, which don't ordinarily fill up a 32-byte cache line, for which the architecture is optimized - when enabled, internal processor buffers combine smaller or partial writes into burstable writes. The chipset may also assemble large PCI bursts from data stored in burst buffers if the bus is not available. Before SP6, NT did not turn this on for the Athlon.


Assign IRQ for VGA
If enabled, the BIOS will assign an IRQ for the VGA card, as most modern cards do. It's for the 3D features of a bus mastering card, like the Matrox Mystique, but it may allow an AGP card to share an IRQ with the PCI 1 slot. Disabling releases the IRQ for another device, or reserves it for PCI 1.


The AGP memory aperture is the range of PCI memory address space used by an AGP card for 3D support, in which host cycles are forwarded to the card without translation, giving extra speed. It is the amount of memory the GART (Graphics Address Re-mapping Table) can see, which makes the processor on the video card see the card memory and is that specified here as one continuous block. This also determines the maximum amount of system RAM allocated to the graphics card for texture storage, so is a combination of card and system memory used as a total (this is done because video memory is expensive). However, the memory isn't actually in one block, except by coincidence - it is assembled from 4K memory pages scattered around the memory map.

There is no universally correct setting, but double your AGP memory size, and add 12 Mb for virtual addressing. The doubled amount is for write combining. If you specify too little, you will get  paging to hard disk, and you may get errors if you specify too much. The default of 64 Mb is usually OK for most drivers, and it's only used when needed, if you have such a card, for which check with the manufacturer. This setting is not performance related, and neither does it affect 3DFX cards, as they do not support AGP texturing. More info on AGP at


PCI Memory Burst Write
When enabled, CPU write cycles are interpreted as the PCI burst protocol (by the PCI bus), meaning that back-to-back sequential CPU memory write cycles addressed to PCI will be translated into (fast) PCI burst memory write cycles. This directly improves video performance when consecutive writes are initiated to a linear graphics frame buffer.


PCI Mem Line Read
When enabled, PCI Memory Line Read commands fetch full cache lines. Otherwise, partial reads are done.


PCI Mem Line Read Prefetch
When enabled, PCI Memory Line Read commands fetch a full cache line and a prefetch of up to three more. Prefetching does not cross 4K address boundaries. This setting is irrelevant if PCI Mem Line Read (above) is disabled.


Open Sesame
The ways of getting into a BIOS are many and varied; if your PC doesn't actually need a setup disk, you could try any one of the following, in no particular order (of course, whether they work or not often depends on which keyboard driver you have loaded). Thanks to pellefsen, jfreeman, bruff, snafu, tankman, jdm17, sanity, pr, julesp, halftone, apel, and markjones, all on for some of the following:

o Press del during boot (AMI, Award).
o Press Esc during boot-Toshiba.
o Press F1 during boot (Toshiba; some Phoenix; Late PS/1 Value Point and 330s).
o Press F2 during boot (NEC, newer Phoenix).
o Press F10 when square in top RH corner of screen (Compaq).
o Press Ins during boot-IBM PS/2 with reference partition.
o Press reset twice-some Dells.
o Ctrl Alt Enter-Dell.
o Ctrl Alt ?-some PS/2s, such as 75 and 90.
o Ctrl-Esc
o Ctrl Ins-some PS/2s when pointer at top right of screen.
o Ctrl Alt Esc -AST Advantage, Award, Tandon, older Phoenix.
o Ctrl Alt +
o Ctrl Alt S-older Phoenix.
o Ctrl Alt Ins (Zenith, Phoenix)
o Ctrl S (Phoenix).
o Ctrl Shift Esc-Tandon 386.
o Shift Ctrl Alt + Num Pad del-Olivetti PC Pro.
o Setup disk-Old Compaqs, Epson (Gemini), IBM, IBM PS/2, Toshiba, old 286s.
o Fn+F2. AST Ascentia 950N

  Setting Up For Performance
Setting up the BIOS to get the best performance (or rate of data transfer around the machine, at least) involves quite a bit of tedious trial and error, rebooting your system time and again to check the results. For this reason, you want a quick and easily used diagnostic program (e.g. the Core hard disk performance test, or the Quake 1.06 benchmark) with which to check your hard disk data transfer rate, or whatever. It doesn't matter about the figures; they will only be used for comparison purposes. In fact, increases in performance will often not be indicated by the figures, but by your own judgments.

Performance between motherboards can be affected by the chipset, or who makes the support chips for the CPU; so much so that a 200 MHz Pentium with a slow chipset can be seriously outperformed by a 133 MHz one supported properly. The Advanced Chipset Setup helps you to tweak the settings provided if required. You want to concentrate on the following areas:

   a.. Burst Mode-used on 486s and above, where a single address cycle precedes four data cycles; 4 32-bit words can move in only 5 cycles, not 8. You need long bursts with low wait states; 1 wait state during a burst loses half the bandwidth.

    a.. Optimizing Refresh Cycles-for example, Concurrent Refresh allows the CPU to read cache memory during a RAM refresh cycle. This should be the first to be turned off if you get a problem.

    a.. Interleaving-allows memory access whilst other blocks are being refreshed, though you don't have much control over this, and is not so important on newer machines.

    a.. I/O recovery time-that is, the timing parameters of your main board and its relation to cards on the ISA bus (use No, Disabled or the lowest settings for best performance!). Use in preference to increasing bus speeds.

    a.. Shadow RAM-ROM contents are transferred to main memory, which is given the same electronic address as the original ROM, and run much faster.  Not much good with NetWare, and possibly '95 or NT as they use their own drivers.

    a.. Latency, especially on the PCI bus. In other words, how long a PCI card may tie up the bus before releasing it to either another card or the ISA bus. A short latency time means the bus is given up more quickly, which is good for speed but not when you're mastering CDs, where you want long data streams with as few interruptions as possible. 32-64 seem to be best for most PCs.

Take a note of all the settings in your Advanced Chipset Setup (you can use PrtScrn), and vary them one at a time, taking a note of the test results each time. You will probably find, perversely, that relatively high wait states and low bus clock speeds will actually result in better performance because the components are better matched. For example, a 60 MHz bus with a 120 MHz Pentium will run with zero wait states, whereas the 100 MHz version may need one. Just remember that the faster you go, the less stability you have, or, in other words, you can have speed or stability, but not both.

Changing DMA settings often affects reliability rather than performance. Phoenix recommends that the first place to start if you have a problem is to turn off any Hidden or Concurrent Refresh options.

Operating systems like Windows 95/98 (that is, those that supply their own 32-bit drivers) will often override some of these settings, especially when it comes to hard disk operation (PIO, Block Mode) or other I/O operations.


Recovering A Corrupt BIOS
Do this with care...
Generally, all you need is a BIOS chip from a similar motherboard -  although they are specifically made, very often you can use one where the chipset doesn't vary too much, say, between an FX or HX motherboard. It helps if the I/O chip is the same, as well, but all you need to do is be able to boot to DOS so you can change the chip when the machine is running. So, remove the corrupt chip, fit the good one, boot the machine with DOS and swap the chips again. By this time, the BIOS will have been shadowed, and running from RAM, so the machine will still work. Reflash the chip.

Intel motherboards sometimes have a Flash Recovery jumper, which activates a small amount of code in the boot block area (which, luckily, is non-erasable). Put the jumper in the recovery position, start the machine with a bootable diskette, listen to the speaker and watch the floppy access light (there's no video available, due to the size of the code). When you hear a beep and the light comes on, the recovery code is being reloaded. When the light goes out, switch the machine off, put the jumper back to its normal position and continue.

There is a similar procedure with Award-based boards, but you can't do it with a PCI video card installed - replace it with an ISA one first.



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Updated 07/06/04

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