Weekly Tweaks Archive II
Video ROM Shadow C000, 32K
Allows you to
shadow (or electronically move) the contents of the Video ROM at the specified address, e.g.
C000, into extended memory for better performance. The extended memory is then given the same
address so the code thinks it's where it should be, and then write-protected (if you're
programming or debugging you can sometimes set shadowed areas as Read/Write).
ROM instructions are 8-bit, and s-l-o-w—that is, accessed one bit at a time.
Shadowing copies the contents of the ROM into 32-bit (or 16-bit on a 286 or 386SX) memory,
disables the ROM and makes that memory look as if it's in the original location, so the code is
executed faster. However, you will lose a corresponding amount of extended memory.
If your video card has 16K of ROM, shadow at C400 only. If it has 32K (most do),
you should include C000 as well. Shadowed ROMs can also be cached in their new locations through
the Advanced Chipset Setup, although this is not always advisable (see below). Some video
cards can't be shadowed because they use an EEPROM (or flash ROM) to store configuration data,
and you won't be able to change the contents if this is enabled. Never mind! If you've got a
large cache this setting may not be needed anyway.
C000 caching has one drawback, in that it's done in the 486 internal cache,
which cannot be write-protected. Whenever a diagnostic test is done, the program sees there is a
BIOS present, but has no knowledge of the caching, so it will treat the code as being a
non-write-protected BIOS, which is regarded as an error condition. If you get failures in this
area, disable this option.
Today’s video cards use Flash ROM, which is faster, and may negate the need for
this setting. Sometimes, disabling this with such cards can increase graphics performance.
Video BIOS Shadow
See Video ROM Shadow C0000,
Adapter ROM Shadow C800, 16K
with others, this functions in the same way as Video ROM Shadow, above, but refers to
16K blocks of upper memory which cover ROM's on adapter cards, such as hard disk controllers. To
use this item effectively, you need to know what memory addresses your expansion cards use. (but
you could enable them all if you don't know) However, some ROMs don't like being shadowed,
particularly those on hard disk controllers, so the best you can do is experiment. Using this
reduces available extended memory.
System ROM Shadow
Allows the 64K block
of upper memory containing the system BIOS (starting at F000) to be shadowed for better
performance, but only when using DOS or another single-user operating system. Disable for UNIX,
XENIX or similar; they have their own arrangements.
See System ROM Shadow
ROM Shadow above.
Floppy 3 Mode Support
This is for the Japanese
standard floppy, which gets 1.2 Mb onto a 3.5" diskette. Normally disable, unless you have
When this is Enabled,
the BIOS sets its own values for some items, such as the Bus Clock Speed, Fast Cache Write Hit,
Fast Cache Read Hit, Fast Page Mode DRAM, DRAM Wait State, DMA CAS Timing Delay, Keyboard Clock,
etc (the items will vary between motherboards). The important thing to note is that your own
settings will be ignored, so disable this one if you want to play, or have to change any of
the above settings to accommodate a particular card, such as a Bus Logic BT-445S on a 50 MHz 486
IDE 32-bit Transfer
Many local bus interfaces
can combine two 16-bit words into a 32-bit doubleword when reading data to and from the disk,
particularly useful with bus mastering. This is often called 32-bit access, though it's really
32-bit host bus transfers. Either way, more efficient use is made of the bus and CPU, so this may
or may not make much difference if you don’t actually have a bottleneck. This is not the same
as Windows' 32-bit features, which are also misnamed as they just work in protected mode.
If disabled, 16-bit data transfers are used, so performance will be less.
enabled, hard disk data is read twice before request signals are sent to the CPU.
setting can only be enabled if IDE Prefetch Mode is also enabled (below). As far as AMI are
concerned, the WinBIOS will initialize the hard disk firmware for 32-bit I/O, assuming your hard
disk is capable—it refers to the new release of high performance Mode 4 drives.
IDE Prefetch Mode
for IDE drive interfaces that support it. If you are getting drive errors, change the setting to
omit the drive interface where the errors occur. Does not appear when Internal PCI/IDE is
DMA FLOW THRU Mode
Enable this if you
enable write buffers to avoid inconsistencies; this makes the DMA wait until all write buffers
are empty. You won't increase performance by increasing the DMA clock by itself but, since it's
often linked to the bus clock, will increase in sympathy with it. Generally, only floppies use
DMA anyway, but some tape streamers and sound cards do.
When CAS is low, RAS is made high,
then low. Since CAS is low before RAS, you get a CBR refresh. The "hidden" part comes
from the fact that data out stays on the line while refresh is being carried out, otherwise this
is the same as CBR. If CAS is hidden, you can eliminate a CPU cycle, but the CPU can also
maintain the cache status if the system starts power saving. Best system performance is naturally
obtained with this enabled, but expect to disable it if you are using 4Mb DRAMs (or certain
SIMMs), or you get problems. Most of the effects of this setting are masked if you have a cache.
Non-cacheable Block-1 Base
The base address of the
above block must be a multiple number of its size; e.g. if 512K was selected above, the starting
address should be a multiple of 512K. In other words, if the previous option has a number other
than Disable, this option will increment by that number.
Non-cacheable Block-1 Size
Depending on the
chipset, this concerns memory regions (including ROMs) not within the 32-bit memory space, e.g.
those on 16-bit expansion cards on the expansion bus (video cards, caching disk controllers, etc)
that should not be cached because RAM on them is updated by the card itself, and the main board
cache controller can't tell if the contents change. These devices communicate as if they were
DRAM memory (that is, they are memory-mapped), which means they need to react in real time and
would be seriously affected by caching. You would also use this to lock out any ROMs you can't
otherwise disable caching for; certain caching IDE controllers use a space at the top end of base
memory for hard disk details, and therefore cause timing problems if the information is cached;
symptoms include consistent bad sectors when formatting floppies, or a scrambled hard disk.
Also, video cards sometimes use a 1 Mb area in the 16 Mb address space of the ISA
bus so they don't have to bank switch through the usual 64K page (early Video Blaster cards are
notable for this requirement; they won't work in a machine with more than 15 Mb RAM).
You might get a choice of System Bus or Local DRAM. The former produces a hole in
Local DRAM. NCB areas can be separate, contiguous or overlapped. With Asustek cache controllers,
include the video buffer at A000-BFFF. This setting is closely linked to the next.
Note: Some chipsets (e.g. SiS) use this to define non-cacheable regions
only in local DRAM; with them, memory on PCI or VESA add-ons is always non-cacheable. Where
memory space is occupied by both local DRAM and an add-on card, the local DRAM will take priority
(as does VESA over PCI), so disable this to allow access or give priority to the card.
Reset Configuration Data
leave disabled, which retains PnP data in the BIOS. Selecting Yes causes the system to
clear itself and automatically configure all PnP devices at boot up.
Use this to reset
ESCD when you exit setup after installing a new card and you cannot boot.
Affected by the Trigger method.
IRQs can be Level or Edge triggered (see Expansion Cards). Most PCI cards use the former, and ISA
the latter. If you select Edge for the slot concerned, you may also need to set jumpers on the
Use Multi-Processor Specification
motherboards with lots of PCI slots, Specification 1.4 allows extended bus definition. It is
needed to allow a secondary PCI bus to work without a bridge.
CPU Fan Off In Suspend
When enabled, the CPU fan
is shut down when the CPU is put into suspend mode. As with power supplies, frequent starting and
stopping the fan may cause more wear than just letting it run.
Doze Mode Control
Sets the Doze Mode clock speed
to various fractions of normal CPU speed and permits the VGA Display to be enabled or disabled.
The DOS time may be incorrect.
Inactive Mode Control
Sets the Inactive Mode
clock speed to fractions of normal CPU speed or turned off entirely - it also permits the VGA
Display to be enabled or disabled. If 0 clock Speed (STOP CLK) is selected, the CPU cannot
monitor external activities and therefore cannot automatically bring the computer back to normal
based on actions such as keystroke entries.
onboard peripherals will be configured automatically or manually. Use Auto if you think PnP will
work, but Manual is usually best, in which case use Auto first, then set them manually.
LPT Extended Mode
? Standard Parallel Port
? Enhanced Parallel Port (EPP)
? Extended Capability Port (ECP)
? EPP + ECP
SPP is unidirectional, as it was designed for printers, and only 5 of its wires are for input;
bi-directional communications actually use printer status signals. SPP does not need interrupts,
so they can be used for other devices.
EPP and ECP have more wires for input, so are
bi-directional and do need interrupts. ECP defines register formats, allows RLL compression, is
fast and buffered, and allows better communication between the device concerned and the PC.
Expect ECP to use DMA 3. EPP allows devices to be connected in a chain, and was designed more as
a high speed bus, so you could rig up a small network.
ECP was developed by HP and
Microsoft in advance of the IEEE specification defining advanced parallel ports, so EPP is
"more compatible". Both have approximately the same performance, but ECP can run faster
than the maximum data transfer rate.
ECP+EPP (default) allows normal speed operation in
two-way mode. SPP may be helpful if you have printing problems with Windows '95.
Parallel Port EPP Type
Sets one of two
versions of EPP, 1.7 and 1.9. Try the latter first, but be prepared to use the former if you get
problems. See also LPT Extended Mode.
Keyboard Reset Control
If enabled, CPU operations
will be halted before the System Reset signal is actually sent. Put more technically, HALT is
executed before SYSC generates CPU reset from Ctrl-Alt-Del.
Keyboard Clock Select
As with bus speed, this
should end up as standard, in this case 7.25 MHz, so for a 40 MHz CPU, you want CPUCLK/5. You can
often decouple the keyboard clock from the bus clock, so you can run one faster than the other.
Some motherboards give you an option of running at 9.25 MHz, but this is not often a good idea.
The keyboard controller is actually a computer in its own right; at least, it has a
microprocessor, and its own BIOS inside.
Novell Keyboard Management
Normally set to No,
but if you find the keyboard sluggish when using a Novell product, set it for the smallest number
between 1-30 that gives you best performance.
Fast Gate A20 Option
Or Turbo Switch Function,
determines how Gate A20 is used to access memory above 1 Mb, which is usually handled through the
keyboard controller chip (the 8042 or 8742). The 8088 in the original PC would wrap around to
lowest memory when it got to 1 Mb. The problem was that some software addressed low memory by
addressing high memory (WordStar 3.3 would complain loudly if you had too much available!). For
older programs, an AND Gate was installed on CPU address line 20 that could switch to allow
either wrap around to 1 Mb or access to the 16 Mb address space on the 286 by forcing A20 to
zero. A convenient TTL signal from a spare pin on the keyboard controller was used to control the
gate, either through the BIOS or with software that knew about it.
The keyboard controller
is actually a computer in its own right; at least there is a PROM and a microcomputer in it
(hence keyboard BIOS), and it had some spare programming space for code that was left out of the
286. Programs such as Windows and OS/2 enter and leave protected mode through the BIOS, so Gate
A20 needs to be continually enabled and disabled, at the same time as another command to reset
the CPU into the required mode is sent.
Enabling this gives the best Windows
performance, as a faster method of switching is used in place of using the (slower) keyboard
controller, using I/O ports, to optimize the sending of the two commands required; the Fast Gate
A20 sequence is generated by writing D1h to port 64h, and data 02h to port 60h. The fast CPU warm
reset is generated when a port 64h write cycle with data FEh is decoded (see Gate A20 Emulation).
Some BIOSes use Port 92. You will notice very little difference if all your programs
operate inside conventional memory (that is, under DOS). However, this may cause Multiuser DOS
not to boot. If you get keyboard errors, enable this, as the switching is probably going too
fast. One problem can occur with this option in AMI BIOSes dated 2/2/91 and later; it doesn't
always work with the DOS 5.00 version of himem.sys. If you get an error message, disable this. If
the error persists, there is a physical problem with the Gate A20 logic, part of which is
contained in the keyboard BIOS chip, in which case try changing this chip. This is nothing to do
with the Turbo switch on the front of the computer (see below); The alternative heading could be
Turbo Switching Function.
Turbo Switch Function
As above, but could also
enable or disable the system Turbo Switch; that is, if this is disabled (no), computer speed is
controlled through setup or the keyboard. On some machines the 486 internal cache is switched on
or off; on others the CPU clock is altered as well. Others still extend the refresh duration of
DRAM. With power saving systems, you can set the turbo pin to place the system into a power
management Suspend mode instead of changing the speed, in which case the other choice will be
Break Key. Sometimes known as Set Turbo Pin Function.
Gate A20 Emulation
As for Fast Gate A20
Option, but you get the choice of Keyboard Controller (if disabled) or Chipset, which is faster.
This is for programs that use BIOS calls or I/O ports 60/64H for A20 operations, where the
chipset will intercept those commands and emulate the keyboard controller to allow the generation
of the relevant signals (see above). The sequence is to write D1h to port 64h, followed by an I/O
write to 60h with 00h. A fast reset is an I/O write to 64h with 1111XXX0b. Fast means that the
A20 gate is controlled by I/O port 92H where programs use BIOS calls. Both means Gate A20 is
controlled by the keyboard controller and chipset where programs use I/O port 60/64H.
I/O Cmd Recovery Control
If enabled, a minimum of 7
bus clocks will be inserted between any 2 back-to-back I/O commands. This helps with problematic
expansion cards and can affect ROM wait states, DMA and bus timing. Disable this, or set to
Normal or the lowest figure available for best performance. Also known as Timing Parameter
Single ALE Enable
If enabled, single instead of
multiple ALEs (see below) will be activated during data bus access cycles. Yes is compatible with
AT bus specifications, giving less performance (multiple ALE signals during a single bus cycle
effectively increase the bus speed, if the hardware can handle it, so watch out for multiple or
missing characters on the screeen). This sometimes appears in older BIOSes as Quick Mode, and you
might see Extended ALE instead of Multiple. May slow the video if enabled, or you might
get missing characters on screen.
ALE stands for Address Latch Enable, an ISA bus signal
used by 808x processors while moving data inside the memory map; it is used by DMA controllers to
tell the CPU it can move data along the data bus, or that a valid address is posted. Conversely,
they can stop this signal and make the CPU wait while data is moved by the controller, so set to
No for normal use. When the CPU wants data, it places the addresses it wants to look at on the
bus, followed by a control signal to let the memory controller know the address is there, which
then latches the address, decodes it and puts what the CPU wants on the bus, where it can be
latched in turn by the CPU (latch means read).
E0000 ROM belongs to AT BUS
Officially, the E000
area of upper memory is reserved for System BIOS code, together with F000, but many machines
don't use it, so E000 can often be used for other purposes (note, however, that this 64K is
needed to run protected mode software, such as OS/2, or Multiuser DOS, which loads Advanced BIOS
code into it). This will only tend to appear on older machines, as PCI needs it too. It
determines whether access to the E area of upper memory is directed to the system board, or to
the AT bus. Set Yes if you want to use it for anything (e.g. a page frame or a Boot ROM), or if
you're using Multiuser DOS and want the maximum TPA to be available. Can also turn up as E000 ROM
AT Cycle Wait State
This figure represents the
number of wait states inserted before an operation is performed on the AT bus. The effect is to
lengthen the I/O cycle for expansion cards that have a tight tolerance on speed, such as high-end
graphics cards, or you might be overclocking and the ISA bus is tied to the PCI bus speed
and you can't change it. Again, for expansion cards with special requirements (you may get
separate options for 16-bit and 8-bit transfers).
The higher the delay in bus timing,
the slower your system will run; 1 wait state can half the bus speed, and you will also need to
set a higher DMA wait state. To avoid confusion, a private message is sent along the data bus for
16-bit cards, before data is sent. The high part of the target address is sent out first,
so 16-bit cards are alerted as to where instructions are headed. As these are sent out over the
extra 4 address lines on the extended bus (20-23), the only information the cards really
get is which of the 16 possible megabytes is the destination, so 3 of the original 8-bit lines
are duplicated (17-19), narrowing it down to the nearest 128K. Once a card decides the
message is for itself, it places a signal on memcs16, a line on the extended bus, which triggers
a 16-bit signal transfer (without the signal, the message is sent as 8-bit). When the CPU
sees memcs16, it assumes the current access will be to a 16-bit device, and begins to assemble
data so any mismatches are transparent to the CPU and adapter card. The trouble is that there's
no specification governing the amount of time between the advance notice and the actual transfer,
and some cards don't request 16-bit transfers quickly enough, so it gets its data as 8-bit, hence
confusion, and the need for wait states. VGA cards can switch into 8-bit mode automatically, but
many others cannot. I/O operations on the bus generally have an extra wait state compared to
Extra AT Cycle Wait State
16-bit Memory, I/O Wait State
The number of wait
states inserted before 16-bit memory and I/O operations. You can often set this to the smallest
value, since the device itself will activate the I/O-CHRDY signal, which allows it to extend the
bus cycle by itself if required. If the bus is running faster than 8 MHz, 2 is generally safest.
Try between 1-2 when running the bus slower.
8-bit Memory, I/O Wait State
If you get bus
timing problems, this setting will insert wait states when accessing devices on the bus. You can
often set this to the smallest value, since the device itself will activate the I/O-CHRDY signal,
allowing it to extend the bus cycle by itself if required. If the bus is running faster than 8
MHz, 1 is generally safest. Try 0 when running the bus slower.
Cache Read Hit Burst
Burst Mode is a 486
function for optimising memory fetches if you need to go off-chip, which works by reading groups of
four double-words in quick succession, hence burst. The first cycle has to cope with the start
address as well as its data, so it takes the longest (the other three addresses are deduced). Once
the transfer has been started, 4 32-bit words could therefore move in only 5 cycles, as opposed to
8, by interleaving the address and data cycles after the first one. For this, you need fast RAM
capable of Page Mode. This setting determines the number of cycle times to be inserted when the CPU
reads data from the external (Level 2) cache, when it can't catch up with the CPU (you may see
similar figures allocated to L1 cache, on chip).
The Secondary Cache Read Hit can be
set to 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 (3-1-1-1 means the first 32-bit word needs three clock
cycles and the remainder need one, giving a total of 6 clock cycles for the operation). Performance
is affected most by the first value; the lower the better; 2-1-1-1 is fastest. You can alter it
with the Cache Read Hit 1st Cycle WS setting. This will have no effect if all the code executes
inside the chip. For example, the setting for 33 MHz may need to be changed to 3-2-2-2 if you only
have 128K, or with Asynchronous SRAM. The following may be useful as a starting point (1 bank
cache/2 banks cache): Item 20 MHz 25 MHz 33 MHz 50 MHz SRAM Read Burst Control 3222/2111 3222/2111
3222/3111 3222 SRAM Write Wait States 0W 0W 1/0W 1W DRAM Write Wait States 0W 0W 1W 1W DRAM Read
Wait States 1W 2W 2W 3W RAS# to CAS# Delay 1 Sysclk 1 Sysclk 1 Sysclk 2 Sysclk Pentiums can perform
Burst Writes as well as Burst Reads, so you might have a separate selection for these. 4-1-1-1 is
Cache Burst Read Cycle Time
See Cache Read Hit
Burst. Automatically set to 2T if only one bank of Level 2 cache is available, that is, the whole
cycle takes place inside 2 T-states.
SRAM Read Timing
Similar to Cache Read Hit Burst.
Relates the number of cycles taken for the SRAM address signal to the number allocated for the
actual read. 2-1-1-1 is the default.
DRAM Page Mode Operation
Page mode allows faster timing on
consecutive memory accesses within a single DRAM page. Mostly, page mode is invoked automatically
if the DRAM supports it.
CPU to DRAM Page Mode
Determines whether a DRAM memory page is
held open after a memory access, as those to open pages can be between 30-40% faster than to
closed pages, because they don't need pre-charging.
Enabling this keeps all pages open.
Disabling only opens them during burst operations, etc, when subsequent accesses will be to the
Possibly related to 4-way memory
interleaving. Enabled is best for performance.
Force Updating ESCD
If enabled, the ESCD area in Upper
Memory (for PnP information concerning IRQ, DMA, I/O and memory) will be updated once, then this
setting will be disabled automatically for the next boot.
Use if you have installed a new card and the subsequent reconfiguration causes a
serious conflict of resources (the OS may not boot as a result). The BIOS will then reallocate
S.M.A.R.T. for Hard Disks
& Reporting Technology, a feature of EIDE. Allegedly allows a drive to monitor itself and
report to the host (through management software) when it thinks it will fail, so network managers
have time to order spares. In fact, the management software sits between the BIOS and the hard
drive and allows the BIOS to look at the data and decide whether or not to give you warning
messages. This has nothing to do with performance, but convenience. Unfortunately, although Win
95 OSR2 and OS/2 (Merlin) are SMART aware, many failures cannot be sensed in advance. Some
utilities can check the status of a drive - Micro House EZ-S.M.A.R.T. and Symantec S.M.A.R.T.
Since this system allows the monitoring of hard drives over a network, you will
get extra packets not necessarily controlled by the operating system - if you get mysterious
reboots and crashes, disable this. If you get problems with Win 98, check out article Q199886 in
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