Weekly Tweaks Archive IV
CPU Internal Core Speed
When you select whatever
speed your CPU should be running at, the correct host bus speed and bus frequency multiplier will
automatically be selected. However, if you choose the Manual setting, as when overclocking, you
will also see:
CPU Host Bus Frequency
Whatever you want the bus speed
CPU Core: Bus Freq. Multiple
Whatever you want the CPU
multiplier to be
CPU Core Voltage
If you choose the Default setting,
it will be set automatically.
CPU Clock Failed Reset
If you enable this, and your
system crashes three times because your overclocking is too much, your CPU speed will
automatically be reset to twice the bus speed.
CIH Buster Protection
Protects against viruses that try to
destroy the BIOS.
Boot Sector Virus Protection
All it does is warn
you when attempts are made to write to your boot sector or partition table, so it can be annoying
when you see the error message every few seconds or so while trying to do something legitimate.
Actually, it's useless for those drives that have their own BIOS in the controller (ESDI/SCSI).
-Disable when using Multi-user DOS, or installing software.
-Only available for
operating systems such as DOS that do not
trap INT 13.
See Boot Sector Virus Protection (Award).
ChipAway Virus On Guard
Guards against boot virus
threats early in the boot cycle, before they have a chance to load.
Report no FDD for Win 95
Set to Yes if using Windows 95/98 without a floppy to
release IRQ6 (this is required to pass Windows 95/98's SCT test and get the logo).
Also disable the Onboard FDC Controller in the Integrated Peripherals screen.
CPU L2 cache ECC Checking
If enabled, data is checked as it passes through the L2 cache,
which reduces performance slightly. However, you must be running a fastish PII or above to see
Acer ID Strings
In the bottom left hand corner of the
The first 2 characters after ACR identify the
motherboard. The last few are
the BIOS revision. The ones before that are the date (e.g.
ID Motherboard Product
05 X1B Altos 19000
07 M7 Altos 900/M and 9000/M
1A M3A Altos 300
1B V35 Power
22 V50LA-N Acros, Power
24 M9B Altos
25 V55LA Acros, Power, Aspire
29 V60N AcerPower
2F M11A Altos 900/Pro
V56LA Acros, Power, Aspire
33 V58LA Acros, Power, Aspire
35 V35N Acros, Power
Altos 920 and 9100
4B V55LA-2M Acros, Power, Aspire
5A X3 Altos 19000 Pro 4
63 V58 Entra
67 V65LA Acros, Power
6B A1G4 Acros
6D V20 AcerPower
M5 Altos 7000P
8F M3 (SCSI) Altos 9000
8F M3-EIDE AcerPower, AcerPower 590
-2 Acros, Power
9A V30, -2 Acros, Power
9C V12LC, -2X Acros, Power, Aspire
A cut-down version of the PII aimed at the low-cost market, initially supplied without an L2
cache, which prompted the unofficial name of DeCeleron. It was subsequently reissued with 128K of
L2 cache running at processor speed, resulting in a chip that has gained some respect, especially
as it rivals the PII in many areas. It started off using Slot 1, but now uses Socket 370, with
the provision that, from 533 MHz, Coppermine (.18 micron) technology was used and wonít
necessarily fit your socket, as some of the pinouts were changed. Converters are available,
though, including those to allow Socket 370 chips to use Slot 1. Although the chip is as fast, if
not faster, than PIIs or even PIIIs, its front side bus only runs at 66 MHz. Also, you will not
be able to upgrade a socket 370 Celeron to a Pentium III (if for no other reason, they donít
use the same vcoltages). Also, be aware that the 400 and 433 MHz versions use fixed clock
multipliers of 6 and 6.5, which means 600 and 650 if you try to use an FSB of 100 MHz.
Cyrix A20M Pin
Cyrix chips need special BIOS
handling, if only because their 386 version has a cache (Intel's doesn't), and it may have
trouble keeping the cache contents up to date if any part of the PC is allowed to operate by
itself, in this case, the keyboard controller toggling the A20 gate. The A20M signal can
be raised separately by the BIOS to tell the CPU the current state of the A20 gate.
This also allows the CPU's internal cache to cache the first 64K of each Mb in real mode (the
gate is always open in protected mode), and is fastest.
Cyrix Pin Enabled
As above, but refers to DMA and the
FLUSH pin on the CPU, which invalidates the cache after any DMA, so the contents are updated from
main memory, for consistency. If you can't set the FLUSH pin, increase the refresh interval and
use Hidden Refresh
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