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Weekly Tweaks Archive VI

System Monitor Setup

Fan Speed
The speed of the fan connected to the headers listed here. The value assumes 2 pulses per revolution and should therefore be used as a relative figure.

Voltage Values
Shows the current values on the motherboard. +3.3v, +5v, +12v, -12v and -5vcome from the ATX power supply. VTT (+1.5) is GTL Termination Voltage from the on-board regulator and VCCVID (CPU) is the CPU core voltage from the on-board switching power supply.

VCCVID(CPU) Voltage, VTT(+1.5V) Voltage
The current value of all significant voltages on the motherboard. VTT is the GT Termination voltage from the onboard regulator. VCCVID is the CPU core voltage from the power supply.

I/O Plane Voltage
When the CPU Power Plane is set to Dual Voltage, you can choose the I/O or external voltage. Otherwise, this setting will not be present.

Core Plane Voltage
When the CPU Power Plane is set to Dual Voltage, you can choose the Core voltage. Otherwise, this setting will not be present.

Plane Voltage
When the CPU Power Plane is set to Single Voltage, you can choose the voltage, which should be correct for your CPU. Otherwise, this setting will not be present.

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Fast R-W Turn Around
Reduces the delay between the CPU's first read from RAM and subsequent write - in other words, reduces the switch time. Enabling increases performance at the risk of stability.

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PCI Dynamic Bursting
When enabled, every write transaction goes to the write buffer, and sent when there are enough to justify a single burst.

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PCI Delayed Transaction
Uses a 32-bit posted write buffer to cope with the very much slower ISA bus, and allow the PCI bus to get on with something else while it's waiting. Enabled supports PCI 2.1, and is best for performance. If you haven't got an ISA bus, you shouldn't need it, but sometimes items (such as embedded IDE connections) are on the ISA bus anyway - you just don't see the slots.

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PCI #2 Access #1 Retry
Enables PCI #2 Access in #1 attempts. When the CPU to PCI Write Buffer is enabled (normal), writes to the PCI bus are written to it instead, which frees the CPU. The writes take place at the next bus cycle. If they fail, and this is enabled, attempts will continually be made until success is achieved, with an obvious tax on performance if you have a slow PCI device. Disabling forces the buffer to flush its contents and register the transaction as failed, making the CPU do the write again to the buffer.

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CPU Level 2 Cache ECC Checking
This setting enables or disables ECC checking by the L2 cache, to detect and correct single-bit errors in data stored there. Mainly for use in file servers, where small errors would be spread round the network, ECC (Error Correction Code) allows the correction of memory errors of one bit, for which you need DIMMs with an extra 8 bits of bandwidth on board (they have an x72 designation, as opposed to x64).

It works with the memory controller to add bits to each bit sent to memory which are decoded to ensure that data is valid, and used to duplicate information should it be necessary. Although similar to parity, there is only a penalty cycle when a 1-bit error is detected, so there is no performance hit during normal operations (multi-bit errors are detected but not corrected). You can use ECC chips in a non-ECC board - you just won't get the benefits.

SDRAM Configuration
Either Disabled or By SPD.

SPD (Serial Presence Detect) refers to a little EEPROM on the DIMM that holds data relating to its performance, which is checked during startup to match timings, required for the PC100 standard as things are a little tight at that speed. In other words, it talks to the BIOS to coordinate memory timings between main memory and L2 cache as, although the two systems may be running at the same frequency, there may still be a mismatch.

Do not accept its findings as gospel - the EEPROM is not write protected and can be overwritten with false specifications. In addition, if the manufacturer is unrecognized, you will get the slowest settings anyway and, very often, when the manufacturer is recognized, good parameters are assumed without checking.

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Video Memory Cache Mode
Video memory is not normally cacheable as the L2 cache would overflow. When the CPU calculates 3D instructions, thereby using floating point operations, every data point needs to be written to the local frame buffer, that is, the memory on the card. Unfortunately, the CPU can only either write or calculate at any one time, so write cycles interfere with floating point operations, reducing them by half as they can only use every other cycle.

Write combine buffers in the CPU can store such data temporarily and release it in burst mode, increasing graphics performance, which depends on the size of the buffers. With the CXT revision of the K6-2 and the K6-III, AMD added two WC buffers, and proper addressing of them could boost graphics by as much as 30%. The Athlon has four 64 bit buffers that can be placed over the card memory for data and hardware acceleration. Compared to the PII/III, this can execute out of order writes in ascending and descending order, so 3D floating point operations can almost be doubled.

Available settings in the ASUS A7V BIOS are either uncached (UC) or uncached speculative write combining (USWC). The latter needs support from graphics hardware and drivers, as some guesswork on behalf of the machine is involved.

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Bank X/Y DRAM Timing
An older name for RAS to CAS Delay. It is actually a mixture of several settings, including bank interleaving. The selections are SDRAM 8-10ns, Normal, Medium, Fast and Turbo. However, only Normal and Turbo seem to make a difference. The former enables 4-way bank interleaving and the latter reduces RAS to CAS delay down to 2T.

SDRAM SRAS Precharge Delay: tRP
The number of cycles needed to move data back to where it came from to close the bank or page before the next bank activate command can be issued. 

SDRAM Addr A Clk Out Drv 
Believed to have something to do with the drive strength of the output clock on a memory bank. Set high for stability.

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S2K I/O Compensation
Concerns the signal strength on the S2K bus, which is a point-to-point bus from the memory controller to the CPU (Athlon), licensed from Alpha. It uses its own protocol to deliver an effective 200 MHz data transfer rate.

Increase the voltage for more stability when overclocking.



DOS Flat Mode
For using the DOS method of memory addressing, where every memory address is a real, for better stability (see the Memory chapter). Windows uses extended memory this way automatically, so a setting like this in the BIOS would be for when you are using software that needs it to run. Using this, therefore, memory addresses consist of one piece, rather than the segment and offset.

The result is safer addressing, and the possibility of creating and running larger programs.



Memory Termination
This is like terminating the (high speed) memory bus in a similar way to SCSI (it uses things like termination voltage regulators), that is, it stops stray signals bouncing around all over the place. As such, it may be a fix for ghost memory, where the board thinks it has more memory installed than is actually there (2 modules are shown, where you only have one, for example).

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Updated 07/06/04

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